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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:27:32 08/12/2015 
-- Design Name: 
-- Module Name:    dtrigger - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dtrigger is
    Port ( din : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           dout : out  STD_LOGIC;
           ndout : out  STD_LOGIC);
end dtrigger;

architecture Behavioral of dtrigger is

signal dout_signal : STD_LOGIC;
signal ndout_signal : STD_LOGIC;

begin

process(clk)
begin
	if (clk'event and clk='1') then
		dout_signal <= din;
		ndout_signal <= din nand '1';
	end if;
end process;

dout <= dout_signal;
ndout <= ndout_signal;

end Behavioral;

